Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Positive Edge
Polarity
Inverting, Non-Inverting
Mounting Type
Surface Mount
Package Type
VSSOP
Pin Count
8
Set/Reset
Yes
Number of Elements per Chip
1
Maximum Propagation Delay Time @ Maximum CL
3.5 ns @ 3.3 V
Dimensions
2.1 x 2.4 x 0.85mm
Maximum Operating Supply Voltage
5.5 V
Height
0.85mm
Propagation Delay Test Condition
50pF
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
2.1mm
Width
2.4mm
Minimum Operating Supply Voltage
1.65 V
Country of Origin
Thailand
Product details
74LVC1G/74LVC2G Family
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
€ 6.90
€ 0.69 Each (In a Pack of 10) (Exc. VAT)
€ 8.14
€ 0.814 Each (In a Pack of 10) (inc. VAT)
10
€ 6.90
€ 0.69 Each (In a Pack of 10) (Exc. VAT)
€ 8.14
€ 0.814 Each (In a Pack of 10) (inc. VAT)
Stock information temporarily unavailable.
10
Stock information temporarily unavailable.
| Quantity | Unit price | Per Pack |
|---|---|---|
| 10 - 90 | € 0.69 | € 6.90 |
| 100 - 240 | € 0.63 | € 6.30 |
| 250+ | € 0.63 | € 6.30 |
Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
D Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Positive Edge
Polarity
Inverting, Non-Inverting
Mounting Type
Surface Mount
Package Type
VSSOP
Pin Count
8
Set/Reset
Yes
Number of Elements per Chip
1
Maximum Propagation Delay Time @ Maximum CL
3.5 ns @ 3.3 V
Dimensions
2.1 x 2.4 x 0.85mm
Maximum Operating Supply Voltage
5.5 V
Height
0.85mm
Propagation Delay Test Condition
50pF
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
2.1mm
Width
2.4mm
Minimum Operating Supply Voltage
1.65 V
Country of Origin
Thailand
Product details
74LVC1G/74LVC2G Family
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS


