Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
Buffer
Number of Channels
2
Schmitt Trigger Input
Yes
Input Type
Schmitt Trigger
Output Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-88
Pin Count
6
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
13.1ns
Maximum Operating Supply Voltage
5.5 V
Dimensions
2.2 x 1.35 x 1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
2.2mm
Height
1mm
Width
1.35mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
€ 32.00
€ 0.16 Each (Supplied on a Reel) (Exc. VAT)
€ 37.76
€ 0.189 Each (Supplied on a Reel) (inc. VAT)
Production pack (Reel)
200
€ 32.00
€ 0.16 Each (Supplied on a Reel) (Exc. VAT)
€ 37.76
€ 0.189 Each (Supplied on a Reel) (inc. VAT)
Production pack (Reel)
200
Stock information temporarily unavailable.
Please check again later.
Quantity | Unit price | Per Reel |
---|---|---|
200 - 360 | € 0.16 | € 6.40 |
400 - 960 | € 0.16 | € 6.40 |
1000 - 1960 | € 0.13 | € 5.20 |
2000+ | € 0.13 | € 5.20 |
Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
Buffer
Number of Channels
2
Schmitt Trigger Input
Yes
Input Type
Schmitt Trigger
Output Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-88
Pin Count
6
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
13.1ns
Maximum Operating Supply Voltage
5.5 V
Dimensions
2.2 x 1.35 x 1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
2.2mm
Height
1mm
Width
1.35mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS