Texas Instruments SN74LVC240ADW Octal-Channel Buffer & Line Driver, 3-State, Inverting, 20-Pin SOIC
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Line Driver
Number of Channels per Chip
8
IC Type
Buffer & Line Driver IC
Input Type
Single Ended
Output Type
3 State
Polarity
Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
20
Maximum High Level Output Current
-24mA
Maximum Low Level Output Current
24mA
Maximum Propagation Delay Time @ Maximum CL
7.5 ns @ 2.7 V
Dimensions
12.8 x 7.52 x 2.35mm
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
3.6 V
Propagation Delay Test Condition
50pF
Country of Origin
Malaysia
Product details
74LVC Family Inverters & Buffers, Texas Instruments
Texas Instruments range of Inverters and Buffers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
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P.O.A.
25
P.O.A.
25
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Line Driver
Number of Channels per Chip
8
IC Type
Buffer & Line Driver IC
Input Type
Single Ended
Output Type
3 State
Polarity
Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
20
Maximum High Level Output Current
-24mA
Maximum Low Level Output Current
24mA
Maximum Propagation Delay Time @ Maximum CL
7.5 ns @ 2.7 V
Dimensions
12.8 x 7.52 x 2.35mm
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
3.6 V
Propagation Delay Test Condition
50pF
Country of Origin
Malaysia
Product details
74LVC Family Inverters & Buffers, Texas Instruments
Texas Instruments range of Inverters and Buffers from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22