Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Latch Mode
Transparent
Latching Element
D Type
Number of Bits
8bit
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
20
Dimensions
6.5 x 4.4 x 1.15mm
Height
1.15mm
Length
6.5mm
Maximum Operating Temperature
+85 °C
Maximum Operating Supply Voltage
3.6 V
Width
4.4mm
Minimum Operating Supply Voltage
1.65 V
Minimum Operating Temperature
-40 °C
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
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€ 0.48
Each (In a Pack of 10) (Exc. Vat)
€ 0.566
Each (In a Pack of 10) (Including VAT)
10
€ 0.48
Each (In a Pack of 10) (Exc. Vat)
€ 0.566
Each (In a Pack of 10) (Including VAT)
10
Buy in bulk
quantity | Unit price | Per Pack |
---|---|---|
10 - 40 | € 0.48 | € 4.80 |
50 - 90 | € 0.45 | € 4.50 |
100 - 240 | € 0.42 | € 4.20 |
250 - 490 | € 0.39 | € 3.90 |
500+ | € 0.36 | € 3.60 |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Latch Mode
Transparent
Latching Element
D Type
Number of Bits
8bit
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
20
Dimensions
6.5 x 4.4 x 1.15mm
Height
1.15mm
Length
6.5mm
Maximum Operating Temperature
+85 °C
Maximum Operating Supply Voltage
3.6 V
Width
4.4mm
Minimum Operating Supply Voltage
1.65 V
Minimum Operating Temperature
-40 °C
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22